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MCP6241/2
50 A, 650 kHz Rail-to-Rail Op Amp
Features
* * * * * * Gain Bandwidth Product: 650 kHz (typ.) Supply Current: IQ = 50 A (typ.) Supply Voltage: 1.8V to 5.5V Rail-to-Rail Input/Output Extended Temperature Range: -40C to +125C Available in 5-pin SC-70 and SOT-23 packages
Description
The Microchip Technology Inc. MCP6241/2 operational amplifiers (op amps) provide wide bandwidth for the quiescent current. The MCP6241/2 has a 650 kHz Gain Bandwidth Product (GBWP) and 77 (typ.) phase margin. This family operates from a single supply voltage as low as 1.8V, while drawing 50 A (typ.) quiescent current. In addition, the MCP6241/2 family supports rail-to-rail input and output swing, with a common mode input voltage range of VDD + 300 mV to VSS - 300 mV. These op amps are designed in one of Microchip's advanced CMOS processes.
Applications
* * * * * * Automotive Portable Equipment Photodiode (Transimpedance) Amplifier Analog Filters Notebooks and PDAs Battery-Powered Systems
Package Types
MCP6241 SOT-23-5
VOUT 1 VSS 2 VIN+ 3
- + +
MCP6241R SOT-23-5
5 VDD VOUT 1 VDD 2 4 VIN- VIN+ 3
- +
Available Tools
SPICE Macro Models (at www.microchip.com) FilterLab Software (at www.microchip.com)
(R)
5 VSS
4 VIN-
Typical Application
RG2 VIN2 RG1 VIN1 VDD RX RY RZ - MCP6241 + VOUT RF
MCP6241 PDIP, SOIC, MSOP
NC 1 VIN- 2 VIN+ 3 VSS 4 - + 8 NC 7 VDD 6 VOUT 5 NC
MCP6241U SC-70-5, SOT-23-5
VIN+ 1 VSS 2 VIN- 3
+ -
5 VDD
4 VOUT
MCP6242
PDIP, SOIC, MSOP
VOUTA 1 VINA_ 2 -+ +B A
8 VDD 7 VOUTB 6 VINB_ 5 VINB+
VINA+ 3 VSS 4
Summing Amplifier Circuit
2004 Microchip Technology Inc.
DS21882B-page 1
MCP6241/2
1.0 ELECTRICAL CHARACTERISTICS
Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings
VDD - VSS .........................................................................7.0V All Inputs and Outputs ................... VSS - 0.3V to VDD + 0.3V Difference Input Voltage ....................................... |VDD - VSS| Output Short Circuit Current ..................................continuous Current at Input Pins ....................................................2 mA Current at Output and Supply Pins ............................30 mA Storage Temperature.................................... -65C to +150C Maximum Junction Temperature (TJ) .......................... +150C ESD Protection On All Pins (HBM;MM) ............... 4 kV; 200V
PIN FUNCTION TABLE
Name Function
VIN+, VINA+, VINB+ VIN-, VINA-, VINB- VDD VSS VOUT, VOUTA, VOUTB
Non-inverting Input Inverting Input Positive Power Supply Negative Power Supply Output
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, RL = 100 k to VDD/2 and VOUT VDD/2.
Parameters
Input Offset Input Offset Voltage Extended Temperature Input Offset Drift with Temperature Power Supply Rejection Input Bias Current and Impedance Input Bias Current: At Temperature At Temperature Input Offset Current Common Mode Input Impedance Differential Input Impedance Common Mode Common Mode Input Range Common Mode Rejection Ratio Open-Loop Gain DC Open-Loop Gain (large signal) Output Maximum Output Voltage Swing Output Short-Circuit Current Power Supply Supply Voltage Quiescent Current per Amplifier
Sym
VOS VOS VOS/TA PSRR IB IB IB IOS ZCM ZDIFF VCMR CMRR AOL
Min
-5.0 -7.0 -- -- -- -- -- -- -- -- VSS - 0.3 60 90
Typ
-- -- 3.0 83 1.0 20 1100 1.0 1013||6 1013||3 -- 75 110
Max
+5.0 +7.0 -- -- -- -- -- -- -- -- VDD + 0.3 -- --
Units
mV mV
Conditions
VCM = VSS TA= -40C to +125C, (Note)
V/C TA= -40C to +125C, VCM = VSS dB pA pA pA pA ||pF ||pF V dB dB VCM = -0.3V to 5.3V, VDD = 5V VOUT = 0.3V to VDD - 0.3V, VCM = VSS RL = 10 k, 0.5V Output Overdrive VDD = 1.8V VDD = 5.5V TA = +85C TA = +125C VCM = VSS
VOL, VOH ISC ISC VDD IQ
VSS + 35 -- -- 1.8 30
-- 6 23 -- 50
VDD - 35 -- -- 5.5 70
mV mA mA V A
IO = 0, VCM = VDD - 0.5V
Note:
The SC-70 package is only tested at +25C.
DS21882B-page 2
2004 Microchip Technology Inc.
MCP6241/2
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +1.8 to 5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 10 k to VDD/2 and CL = 60 pF. Parameters AC Response Gain Bandwidth Product Phase Margin Slew Rate Noise Input Noise Voltage Input Noise Voltage Density Input Noise Current Density Eni eni ini -- -- -- 10 45 0.6 -- -- -- Vp-p nV/Hz fA/Hz f = 0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz GBWP PM SR -- -- -- 650 77 0.30 -- -- -- kHz V/s G = +1 Sym Min Typ Max Units Conditions
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +5.5V and VSS = GND. Parameters Temperature Ranges Extended Temperature Range Operating Temperature Range Storage Temperature Range Thermal Package Resistances Thermal Resistance, 5L-SC70 Thermal Resistance, 5L-SOT-23 Thermal Resistance, 8L-PDIP Thermal Resistance, 8L-SOIC Thermal Resistance, 8L-MSOP Note: JA JA JA JA JA -- -- -- -- -- 331 256 85 163 206 -- -- -- -- -- C/W C/W C/W C/W C/W TA TA TA -40 -40 -65 -- -- -- +125 +125 +150 C C C (Note) Sym Min Typ Max Units Conditions
The internal Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150C.
2004 Microchip Technology Inc.
DS21882B-page 3
MCP6241/2
2.0
Note:
TYPICAL PERFORMANCE CURVES
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 100 k to VDD/2 and CL = 60 pF.
20%
Percentage of Occurrences
18% 16% 14% 12% 10% 8% 6% 4% 2% 0%
630 Samples VCM = VSS
CMRR, PSRR (dB)
90
VDD = 5.0V
85
PSRR (VCM = VSS)
80
75
CMRR (VCM = -0.3 V to +5.3 V)
70
-5 -4 -3 -2 -1
-50
-25
Input Offset Voltage (mV)
0 25 50 75 Ambient Temperature (C)
100
125
0
1
2
3
4
5
FIGURE 2-1:
Input Offset Voltage.
FIGURE 2-4: Temperature.
120 Open-Loop Gain (dB)
CMRR, PSRR vs. Ambient
110 100 PSRR, CMRR (dB) 90 80 70 60 50 40 30 20
1.E+01
Gain
CMRR PSRR+
80 60 40 20 0 -20
1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07
-60
Phase
-90 -120 -150 -180
VDD = 5.0V
1.E+02 1.E+03 1.E+04 1.E+05
10
100
1k Frequency (Hz)
10k
100k
0.1
1
-210 10 100 1k 10k 100k 1M 10M Frequency (Hz)
FIGURE 2-2: Frequency.
26% 24% 22% 20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0% 0 6
PSRR, CMRR vs.
FIGURE 2-5: Frequency.
30% Percentage of Occurrences 25% 20% 15% 10% 5% 0% 0.0 0.2 0.3 0.5
Open-Loop Gain, Phase vs.
Percentage of Occurrences
180 Samples VCM = VSS TA = +85C
180 Samples VCM = VSS TA = +125C
0.6
0.8
0.9
1.1
1.2
1.4
1.5
1.7
1.8
Input Bias Current (pA)
Input Bias Current (nA)
FIGURE 2-3:
Input Bias Current at +85C.
FIGURE 2-6:
Input Bias Current at +125C.
DS21882B-page 4
2004 Microchip Technology Inc.
2.0
12
18
24
30
36
42
Open-Loop Phase ()
PSRR-
100
RL = 10.0 k VDD = 5.0V VCM = VDD/2
0 -30
MCP6241/2
Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 100 k to VDD/2 and CL = 60 pF.
10,000 Input Noise Voltage Density (nV/Hz)
20%
Percentage of Occurrences
18% 16% 14% 12% 10% 8% 6% 4% 2% 0%
628 Samples VCM = VSS TA = -40C to +125C
1,000
100
10
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
-12
-10
10
5.0
Frequency (Hz)
Input Offset Voltage Drift (V/C)
FIGURE 2-7: vs. Frequency.
300 Input Offset Voltage (V) 200 100 0 -100 -200 -300 -0.4 -0.2 0.0 0.2 TA = -40C TA = +25C TA = +85C TA = +125C
Input Noise Voltage Density
FIGURE 2-10:
Input Offset Voltage Drift.
700
Input Offset Voltage (V)
650 600 550 500 450 400 350 300 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VDD = 1.8 V
VCM = VSS
VDD = 5.5 V
VDD = 1.8 V 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
4.0
4.5
5.5
Common Mode Input Voltage (V)
Output Voltage (V)
FIGURE 2-8: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 1.8V.
400 Input Offset Voltage (V) VDD = 5.5 V 300 200 100 0 -100 -200 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Common Mode Input Voltage (V) TA = -40C TA = +25C TA = +85C TA = +125C
FIGURE 2-11: Output Voltage.
35 30 25 20 15 10 5 0 -5 -10 -15 -20 -25 -30 -35
Input Offset Voltage vs.
Short Circuit Current (mA)
+ISC
TA = +125C TA = +85C TA = +25C TA = -40C -ISC 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V)
FIGURE 2-9: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 5.5V.
FIGURE 2-12: Output Short-Circuit Current vs. Ambient Temperature.
2004 Microchip Technology Inc.
DS21882B-page 5
12
-8
-6
-4
-2
0.1
1
10
100
1k
10k
100k
0
2
4
6
8
MCP6241/2
Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 100 k to VDD/2 and CL = 60 pF.
0.50 0.45 Slew Rate (V/s) 0.40 0.35 0.30 0.25 0.20 0.15 0.10 -50 -25 0 25 50 75 100 Ambient Temperature (C) 125 Rising Edge, VDD = 5.5 V Rising Edge, VDD = 1.8 V Falling Edge, VDD = 5.5 V Falling Edge, VDD = 1.8 V
120.00 100.00 80.00 60.00 40.00 20.00 0.00
Output Voltage (20 mV/div)
-20.00 RL -9.E+00 -40.00
G = +1V/V = 10 k
1.E+00
1.E+01
2.E+01
3.E+01
Time (1 s/div)
FIGURE 2-13: Temperature.
Output Voltage Headroom (mV) 1,000
Slew Rate vs. Ambient
FIGURE 2-16: Pulse Response.
5.0 4.5
Small Signal Non-Inverting
G = +1V/V
Output Voltage (V) 10m
10
VDD - VOH 100 VOL - VSS 10
4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5
1 0.00001 0.01
0.0001
0.1
0.001
1
10
0.01
100
0.1
1m
1
0.0
-2.E+01 0.E+00
Output Current Magnitude (A)
Time (20 s/div)
2.E+01
4.E+01
6.E+01
8.E+01
FIGURE 2-14: Output Voltage Headroom vs. Output Current Magnitude.
10 Output Voltage Swing (Vp-p) VDD = 5.5 V
FIGURE 2-17: Pulse Response.
80
Large Signal Non-Inverting
Quiescent Current per Amplifier (A)
70 60 50 40 30 20 10 0
VCM = VDD - 0.5V
1
VDD = 1.8 V
TA = +125C TA = +85C TA = +25C TA = -40C
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
0.1 1k 1000
100k 10k 10000 100000 Frequency (Hz)
1M 1000000
Power Supply Voltage (V)
FIGURE 2-15: Frequency.
Output Voltage Swing vs.
FIGURE 2-18: Quiescent Current vs. Power Supply Voltage.
DS21882B-page 6
2004 Microchip Technology Inc.
MCP6241/2
3.0 APPLICATION INFORMATION
- RIN VIN MCP624X + VOUT The MCP6241/2 family of op amps is manufactured using Microchip's state-of-the-art CMOS process and is specifically designed for low-power and generalpurpose applications. The low supply voltage, low quiescent current and wide bandwidth makes the MCP6241/2 ideal for battery-powered applications.
3.1
Rail-to-Rail Input
( Maximum expected VIN ) - V DD RIN -----------------------------------------------------------------------------2 mA V SS - ( Minimum expected V IN ) R IN --------------------------------------------------------------------------2 mA
The MCP6241/2 op amps are designed to prevent phase reversal when the input pins exceed the supply voltages. Figure 3-1 shows the input voltage exceeding the supply voltage without any phase reversal.
6 Input, Output Voltages (V) 5
FIGURE 3-2: Resistor (RIN).
Input Current-Limiting
VIN VOUT
VDD = 5.0V G = +2 V/V
3.2
Rail-to-Rail Output
4 3 2 1 0 -1
0.E+00 1.E+00 2.E+00 3.E+00 4.E+00 5.E+00 6.E+00 7.E+00 8.E+00 9.E+00 1.E+01
The output voltage range of the MCP6241/2 op amps is VDD - 35 mV (min.) and VSS + 35 mV (max.) when RL = 100 k is connected to VDD/2 and VDD = 5.5V. Refer to Figure 2-14 for more information.
3.3
Capacitive Loads
Time (1 ms/div)
FIGURE 3-1: Phase Reversal.
The MCP6241/2 Show No
The input stage of the MCP6241/2 op amps use two differential input stages in parallel. One operates at low common mode input voltage (VCM) and the other at high VCM. With this topology, the device operates with VCM up to 300 mV above VDD and 300 mV below VSS. The Input Offset Voltage is measured at VCM = VSS - 300 mV and VDD + 300 mV to ensure proper operation. Input voltages that exceed the input voltage range (VSS - 0.3V to VDD + 0.3V at 25C) can cause excessive current to flow into or out of the input pins. Current beyond 2 mA can cause reliability problems. Applications that exceed this rating must be externally limited with a resistor, as shown in Figure 3-2.
Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop's phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. A unity-gain buffer (G = +1) is the most sensitive to capacitive loads, but all gains show the same general behavior. When driving large capacitive loads with these op amps (e.g., > 100 pF when G = +1), a small series resistor at the output (RISO in Figure 3-3) improves the feedback loop's phase margin (stability) by making the output load resistive at higher frequencies. It does not, however, improve the bandwidth.
- VIN MCP624X +
RISO VOUT CL
FIGURE 3-3: Output resistor, RISO stabilizes large capacitive loads.
Figure 3-4 gives recommended RISO values for different capacitive loads and gains. The x-axis is the normalized load capacitance (CL/GN), where GN is the circuit's noise gain. For non-inverting gains, GN and the gain are equal. For inverting gains, GN is 1 + |Gain| (e.g., -1 V/V gives GN = +2 V/V).
2004 Microchip Technology Inc.
DS21882B-page 7
MCP6241/2
10k Recommended RISO ()
1.E+04
VIN-
VIN+
VSS
1k
1.E+03
100 10p
1.E+02 1.E+01
Guard Ring
1.E+02 1.E+03 1.E+04
100p 1n 10n Normalized Load Capacitance; CL/GN (F)
FIGURE 3-5: for Inverting Gain.
1.
Example Guard Ring Layout
FIGURE 3-4: Recommended RISO Values for Capacitive Loads.
After selecting RISO for your circuit, double-check the resulting frequency response peaking and step response overshoot. Evaluation on the bench and simulations with the MCP6241/2 SPICE macro model are very helpful. Modify RISO's value until the response is reasonable.
2.
3.4
Supply Bypass
With this op amp, the power supply pin (VDD for single-supply) should have a local bypass capacitor (i.e., 0.01 F to 0.1 F) within 2 mm for good highfrequency performance. It also needs a bulk capacitor (i.e., 1 F or larger) within 100 mm to provide large, slow currents. This bulk capacitor can be shared with other parts.
Non-inverting Gain and Unity-Gain Buffer: a. Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface. b. Connect the guard ring to the inverting input pin (VIN-). This biases the guard ring to the common mode input voltage. Inverting and transimpedance gain amplifiers (convert current to voltage, such as photo detectors): a. Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the op amp (e.g., VDD/2 or ground). b. Connect the inverting pin (VIN-) to the input with a wire that does not touch the PCB surface.
3.5
PCB Surface Leakage
In applications where low input bias current is critical, PCB (printed circuit board) surface leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1012. A 5V difference would cause 5 pA, if current-to-flow. This is greater than the MCP6241/2 family's bias current at 25C (1 pA, typ). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure 3-5.
DS21882B-page 8
2004 Microchip Technology Inc.
MCP6241/2
4.0
4.1
APPLICATION CIRCUITS
Matching the Impedance at the Inputs
4.2
Compensating for the Parasitic Capacitance
To minimize the effect of offset voltage in an amplifier circuit, the impedance at both inverting and noninverting inputs needs to be matched. This is done by choosing the circuit resistor values so that the total resistance at each input is the same. Figure 4-1 shows a summing amplifier circuit.
RG2 VIN2 RG1 VIN1 VDD RX RY RZ - MCP624X + VOUT RF
In analog circuit design, the PCB parasitic capacitance can compromise the circuit behavior; Figure 4-2 shows a typical scenario. If the input of an amplifier sees parasitic capacitance of several picofarad (CPARA, which includes the common mode capacitance of 6 pF, typical) and large RF and RG, the frequency response of the circuit will include a zero. This parasitic zero introduces gain peaking and can cause circuit instability.
VAC
+ MCP624X - RG RF VOUT
VDC
CPARA
CF
RG C F = CPARA * -----RF
FIGURE 4-1:
Summing Amplifier Circuit.
To match the inputs, set all voltage sources to ground and calculate the total resistance at the input nodes. In this summing amplifier circuit, the resistance at the inverting input is calculated by setting VIN1, VIN2 and VOUT to ground. In this case, RG1, RG2 and RF are in parallel. The total resistance at the inverting input is: 1 R VIN - = -------------------------------------------1 1 1 --------- + --------- + ----- R G1 R G2 RF Where: RVIN- = total resistance at the inverting input At the non-inverting input, VDD is the only voltage source. When VDD is set to ground, both RX and RY are in parallel. The total resistance at the non-inverting input is: 1 R VIN + = ------------------------ + R Z 11 ------ + ----- RX RY Where: RVIN+ = total resistance at the inverting input To minimize offset voltage and increase circuit accuracy, the resistor values need to meet the condition: R VIN + = R VIN -
FIGURE 4-2: Effect of Parasitic Capacitance at the Input.
One solution is to use smaller resistor values to push the zero to a higher frequency. Another solution is to compensate by introducing a pole at the point at which the zero occurs. This can be done by adding CF in parallel with the feedback resistor (RF). CF needs to be selected so that the ratio CPARA:CF is equal to the ratio of RF:RG.
2004 Microchip Technology Inc.
DS21882B-page 9
MCP6241/2
5.0 DESIGN TOOLS
Microchip provides the basic design tools needed for the MCP6241/2 family of op amps.
5.1
SPICE Macro Model
The latest SPICE macro model for the MCP6241/2 op amps is available on our web site at www.microchip.com. This model is intended to be an initial design tool that works well in the op amp's linear region of operation at room temperature. See the model file for information on its capabilities. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves.
5.2
FilterLab(R) Software
The FilterLab software is an innovative tool that simplifies analog active-filter (using op amps) design. Available free of charge from our web site at www.microchip.com, the FilterLab software active-filter design tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the macro model to simulate actual filter performance.
DS21882B-page 10
2004 Microchip Technology Inc.
MCP6241/2
6.0
6.1
PACKAGING INFORMATION
Package Marking Information
5-Lead SC-70 Example:
XNN YWW
A57 418
5-Lead SOT-23
5 4
Example: Device MCP6241 BFNN BGNN BHNN
1 2 3
Code
5
4
XXNN
1 2 3
MCP6241R MCP6241U Note:
BF25
Applies to 5-Lead SOT-23.
8-Lead MSOP XXXXXX YWWNNN
Example: 6242E 418256
8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW
Example: MCP6242 E/P256 0418
8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN
Example: MCP6242 E/SN0418 256
Legend:
XX...X YY WW NNN
Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information.
*
Standard marking consists of Microchip part number, year code, week code, traceability code (facility code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please check with your Microchip Sales Office.
2004 Microchip Technology Inc.
DS21882B-page 11
MCP6241/2
5-Lead Plastic Small Outline Transistor Package (LT) (SC-70)
E E1
D p B
n
1
Q1 c A1 L Units Dimension Limits n p A A2 A1 E E1 D L Q1 c B INCHES NOM 5 .026 (BSC) MILLIMETERS* NOM 5 0.65 (BSC) 0.80 0.80 0.00 1.80 1.15 1.80 0.10 0.10 0.10 0.15 A2 A
MIN
MAX
MIN
MAX
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Top of Molded Pkg to Lead Shoulder Lead Thickness Lead Width
.031 .031 .000 .071 .045 .071 .004 .004 .004 .006
.043 .039 .004 .094 .053 .087 .012 .016 .007 .012
1.10 1.00 0.10 2.40 1.35 2.20 0.30 0.40 0.18 0.30
*Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. JEITA (EIAJ) Standard: SC-70
Drawing No. C04-061
DS21882B-page 12
2004 Microchip Technology Inc.
MCP6241/2
5-Lead Plastic Small Outline Transistor (OT) (SOT23)
E E1
p B p1 D
n
1
c A A2
L
A1
Number of Pins Pitch p1 Outside lead pitch (basic) Overall Height A .035 .057 0.90 Molded Package Thickness A2 .035 .051 0.90 Standoff A1 .000 .006 0.00 Overall Width E .102 .118 2.60 Molded Package Width E1 .059 .069 1.50 Overall Length D .110 .122 2.80 Foot Length L .014 .022 0.35 Foot Angle 0 10 0 c Lead Thickness .004 .008 0.09 Lead Width B .014 .020 0.35 Mold Draft Angle Top 0 10 0 Mold Draft Angle Bottom 0 10 0 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. EIAJ Equivalent: SC-74A
Drawing No. C04-091
Units Dimension Limits n p
MIN
INCHES* NOM 5 .038 .075 .046 .043 .003 .110 .064 .116 .018 5 .006 .017 5 5
MAX
MIN
MILLIMETERS NOM 5 0.95 1.90 1.18 1.10 0.08 2.80 1.63 2.95 0.45 5 0.15 0.43 5 5
MAX
1.45 1.30 0.15 3.00 1.75 3.10 0.55 10 0.20 0.50 10 10
2004 Microchip Technology Inc.
DS21882B-page 13
MCP6241/2
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
E E1
p D 2 B n 1
A c A1 (F)
A2
L
Number of Pins Pitch A .043 Overall Height A2 .030 .037 Molded Package Thickness .000 .006 A1 Standoff E Overall Width E1 Molded Package Width D Overall Length L .016 .031 Foot Length Footprint (Reference) F Foot Angle 0 8 c Lead Thickness .003 .009 .009 .016 Lead Width B Mold Draft Angle Top 5 15 5 15 Mold Draft Angle Bottom *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-187
Drawing No. C04-111
Units Dimension Limits n p
MIN
INCHES NOM 8 .026 BSC .033 .193 TYP. .118 BSC .118 BSC .024 .037 REF .006 .012 -
MAX
MIN
MILLIMETERS* NOM 8 0.65 BSC 0.75 0.85 0.00 4.90 BSC 3.00 BSC 3.00 BSC 0.40 0.60 0.95 REF 0 0.08 0.22 5 5 -
MAX
1.10 0.95 0.15
0.80 8 0.23 0.40 15 15
DS21882B-page 14
2004 Microchip Technology Inc.
MCP6241/2
8-Lead Plastic Dual In-line (P) - 300 mil (PDIP)
E1
D 2 n 1 E
A
A2
c
L A1
eB
B1 p B
Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p A A2 A1 E E1 D L c B1 B eB
MIN
INCHES* NOM 8 .100 .155 .130 .313 .250 .373 .130 .012 .058 .018 .370 10 10
MAX
MIN
.140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310 5 5
.170 .145 .325 .260 .385 .135 .015 .070 .022 .430 15 15
MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10
MAX
4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92 15 15
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018
2004 Microchip Technology Inc.
DS21882B-page 15
MCP6241/2
8-Lead Plastic Small Outline (SN) - Narrow, 150 mil (SOIC)
E E1
p
D 2 B n 1
h 45
c A A2
L A1
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p A A2 A1 E E1 D h L c B
MIN
.053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0
INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12
MAX
MIN
.069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15
MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12
MAX
1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057
DS21882B-page 16
2004 Microchip Technology Inc.
MCP6241/2
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Tape and Reel and/or Alternate Pinout -X /XX Examples: a) b) c) d) Extended Temp., 8LD SOIC pkg. MCP6241-E/MS: Extended Temp., 8LD MSOP pkg. MCP6241-E/P: Extended Temp., 8LD PDIP pkg. MCP6241RT-E/OT: Tape and Reel, Extended Temp., 5LD SOT-23 pkg MCP6241UT-E/OT: Tape and Reel, Extended Temp., 5LD SOT-23 pkg. MCP6241UT-E/LT: Tape and Reel, Extended Temp., 5LD SC-70 pkg. MCP6241T-E/OT: Tape and Reel, Extended Temp., 5LD SOT-23 pkg. MCP6242-E/SN: MCP6242-E/MS: MCP6242-E/P: MCP6242T-E/SN: Extended Temp., 8LD SOIC pkg. Extended Temp., 8LD MSOP pkg. Extended Temp., 8LD PDIP pkg. Tape and Reel, Extended Temp., 8LD SOIC pkg. MCP6241-E/SN:
Temperature Package Range
Device:
MCP6241: MCP6241T: MCP6241RT: MCP6241UT: MCP6242: MCP6242T:
Single Op Amp (MSOP, PDIP, SOIC) Single Op Amp (Tape and Reel) (SOT-23) Single Op Amp (Tape and Reel) (SOT-23) Single Op Amp (Tape and Reel) (SC-70, SOT-23) Dual Op Amp (MSOP, PDIP, SOIC) Dual Op Amp (Tape and Reel)
e)
Temperature Range:
E
= -40C to +125C
f)
Package:
LT MS P OT
Plastic Package (SC-70), 5-lead (MCP6241U only) Plastic Micro Small Outline (MSOP), 8-lead Plastic DIP (300 mil Body), 8-lead Plastic Small Outline Transistor (SOT-23), 5-lead (MCP6241, MCP6241R, MCP6241U) SN = Plastic SOIC, (150 mil Body), 8-lead
= = = =
g)
a) b) c) d)
Sales and Support
Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2004 Microchip Technology Inc.
DS21882B-page 17
MCP6241/2
NOTES:
DS21882B-page 18
2004 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
*
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2004, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company's quality system processes and procedures are for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
2004 Microchip Technology Inc.
DS21882B-page 19
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office
2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: www.microchip.com
China - Chengdu
Ming Xing Financial Tower Chengdu 610016, China Tel: 86-28-86766200 Fax: 86-28-86766599
Taiwan
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China - Fuzhou
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Taiwan
Taiwan Branch Taipei City, 104, Taiwan Tel: 886-2-2500-6610 Fax: 886-2-2508-0102
Atlanta
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China - Hong Kong SAR
Metroplaza Kwai Fong, N.T., Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431
Taiwan
Taiwan Branch Hsinchu City 300, Taiwan Tel: 886-3-572-9526 Fax: 886-3-572-6459
Boston
Westford, MA 01886 Tel: 978-692-3848 Fax: 978-692-3821
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Far East International Plaza Shanghai, 200051 Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
Chicago
Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075
EUROPE
Austria
Austria Tel: 43-7242-2244-399 Fax: 43-7242-2244-393
Dallas
Addison Plaza Addison, TX 75001 Tel: 972-818-7423 Fax: 972-818-2924
China - Shenzhen
United Plaza Shenzhen 518033, China Tel: 86-755-82901380 Fax: 86-755-8295-1393
Denmark
Regus Business Centre Ballerup DK-2750 Denmark Tel: 45-4420-9895 Fax: 45-4420-9910
Detroit
Tri-Atria Office Building Farmington Hills, MI 48334 Tel: 248-538-2250 Fax: 248-538-2260
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Foshan City, Guangdong 528303, China Tel: 86-757-28395507 Fax: 86-757-28395571
France
91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Kokomo
Kokomo, IN 46902 Tel: 765-864-8360 Fax: 765-864-8387
China - Qingdao
Fullhope Plaza, Qingdao 266071, China Tel: 86-532-5027355 Fax: 86-532-5027205
Germany
D-85737 Ismaning, Germany Tel: 49-89-627-144-0 Fax: 49-89-627-144-44
Los Angeles
Mission Viejo, CA 92691 Tel: 949-462-9523 Fax: 949-462-9608
India
Divyasree Chambers Bangalore, 560 025, India Tel: 91-80-22290061 Fax: 91-80-22290062
Italy
Milan, Italy Tel: 39-0331-742611 Fax: 39-0331-466781
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India
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Netherlands
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Toronto
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United Kingdom
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Japan
Yokohama, Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122
ASIA/PACIFIC
Australia
Microchip Technology Australia Pty Ltd Sydney, Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755
Korea
Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934
China - Beijing
Wan Tai Bei Hai Bldg. Beijing, 100027, China Tel: 86-10-85282100 Fax: 86-10-85282104
Singapore
Singapore, 188980 Tel: 65-6334-8870 Fax: 65-6334-8850
08/16/04
DS21882B-page 20
2004 Microchip Technology Inc.

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